In the related art, when test patterns for a target circuit designed in a design flow of a semiconductor integrated circuit are generated, the target circuit is divided into a plurality of circuits and the test patterns are generated in parallel with a plurality of computers in some cases in order to shorten a generation time of the test pattern.
For example, there is a known technology for dividing a target circuit so that the numbers of gates of circuits mapped to a plurality of field programmable gate arrays (FPGAs) are equal when the target circuit is mapped to the plurality of FPGAs (for example, see Japanese Laid-open Patent Publication No. 2000-207445).
In the related art, there is a known technology for supplying clock signals to storage elements of a scanning function unit in an opposite order to a data transmission direction when a plurality of clock domains are present in a target circuit and data transmission paths are not mixed between the clock domains (for example, see International Publication Pamphlet No. WO98/49576).
In technologies of the related art, however, when a plurality of blocks included in a target circuit are divided based on a circuit scale such as the number of gates, specific blocks are unevenly distributed to specific divided circuits. In this case, a problem may arise in that characteristics are unequal between the divided circuits.
An object of an embodiment is to provide a circuit division method for test pattern generation, a circuit division program for test pattern generation, and a circuit division device for test pattern generation, configured to equalize characteristics between divided circuits.